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Vanderlei Bonato, Christos Bouganis, Marek Gorgon's Applied Reconfigurable Computing: 12th International PDF

By Vanderlei Bonato, Christos Bouganis, Marek Gorgon

This publication constitutes the refereed complaints of the twelfth overseas Symposium on utilized Reconfigurable Computing, ARC 2016, held in Rio de Janeiro, Brazil, in March 2016.

The 20 complete papers provided during this quantity have been rigorously reviewed and chosen from forty seven submissions. they're geared up in topical headings named: video and snapshot processing; fault-tolerant structures; instruments and architectures; sign processing; and multicore systems.

In addition, the e-book includes three invited papers and eight poster papers on funded RD working and accomplished projects.

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Read Online or Download Applied Reconfigurable Computing: 12th International Symposium, ARC 2016 Mangaratiba, RJ, Brazil, March 22–24, 2016 Proceedings PDF

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Extra resources for Applied Reconfigurable Computing: 12th International Symposium, ARC 2016 Mangaratiba, RJ, Brazil, March 22–24, 2016 Proceedings

Example text

Looking to the IP/CV algorithms, and considering the spatial distribution of PEs over the image area, we can identify a coarse-grained parallelism. In the IP/CV domain, the OpenCV library [1] is one of the most used collection of algorithms. It is used for educational, industrial and scientific purposes, and can be considered as a informal standard. With the increasing number of complex IP/CV commercial applications, the industry identified the need for an IP/CV standard de facto. The Chronos Group [8] released in 2014 the first version of the OpenVX standard.

In this paper, the whole fusion algorithm with the forward and inverse DT-CWTs is written in C++ and executed by the ARM Cortex A9 Processor. The profiling results of the fusion process, as shown in Fig. 1, indicate that the forward and inverse DT-CWT are the most compute- and energy intensive tasks. Therefore, these parts of the algorithm are the ones selected for acceleration in the FPGA. The FPGA fabric available in the ZYNQ device can be made coherent with processor caches using the (Acceleration Coherence Port) ACP and this is the option that has been selected in this paper.

This paper presents a complete video fusion system with hardware acceleration and investigates its performance and energy optimization. The video fusion application is based on the Dual-Tree Complex Wavelet Transforms (DT-CWT). Video fusion combines information from different spectral bands into a single representation and advanced algorithms based on wavelet transforms are compute and energy intensive. In this work the transforms are mapped to a hardware accelerator using high-level synthesis tools for the FPGA resulting in an increase of performance of the system by a factor of 3.

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